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Features
* Read Access Time - 200 ns * Automatic Page Write Operation * * * * * * * *
- Internal Address and Data Latches for 256 Bytes - Internal Control Timer Fast Write Cycle Time - Page Write Cycle Time - 10 ms Maximum - 1 to 256 Byte Page Write Operation Low Power Dissipation - 80 mA Active Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology - Endurance: 10,000 Cycles - Data Retention: 10 Years Single 5V 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-Wide Pinout
4-Megabit (512K x 8) Paged Parallel EEPROMs AT28C040
Description
The AT28C040 is a high-performance electrically erasable and programmable read only memory (EEPROM). Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel's advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 440 mW. (continued)
Pin Configurations
Pin Name A0 - A18 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect LCC Top View
A15 A16 A18 NC NC NC VCC WE NC A17 A14 A18 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
SIDE BRAZE, FLATPACK Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3
A0 I/O0 I/O1 I/O2 VSS NC I/O3 I/O4 I/O5 I/O6 I/O7
18 19 20 21 22 23 24 25 26 27 28
A12 A7 A6 A5 NC NC NC A4 A3 A2 A1
7 8 9 10 11 12 13 14 15 16 17
6 5 4 3 2 1 44 43 42 41 40
39 38 37 36 35 34 33 32 31 30 29
A13 A8 A9 A11 NC NC NC NC OE A10 CE
Rev. 0542B-10/98
1
The AT28C040 is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by
DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmel's AT28C040 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 256 bytes of EEPROM for device identification or tracking.
Block Diagram
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55C to +125C Storage Temperature ..................................... -65C to +150C All Input Voltages (including NC pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
AT28C040
AT28C040
Device Operation
READ: The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems. BYTE WRITE: A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE: The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within 150 s (t BLC ) of the previous byte. If the t BLC limit is exceeded, the AT28C040 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page write operation, A8 - A18 must be the same. The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. DATA POLLING: The AT28C040 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT: In addition to DATA Polling, the AT28C040 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. DATA PROTECTION: If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. Atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. HARDWARE PROTECTION: Hardware features protect against inadvertent writes to the AT28C040 in the following ways: (a) VCC sense - if VCC is below 3.8V (typical) the write function is inhibited; (b) V CC power-on delay - once VCC has reached 3.8V the device will automatically time out 5 ms (typical) before allowing a write: (c) write inhibit - holding any one of OE low, CE high or WE high inhibits write cycles; (d) noise filter - pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. SOFTWARE DATA PROTECTION: A software controlled data protection feature has been implemented on the AT28C040. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28C040 is shipped from Atmel with SDP disabled. SDP is enabled when the host system issues a series of three write commands; three specific bytes of data are written to three specific addresses (refer to Software Data Protection Algorithm). After writing the 3-byte command sequence and after tWC, the entire AT28C040 will be protected against inadvertent write operations. It should be noted that once protected, the host can still perform a byte or page write to the AT28C040. To do so, the same 3-byte command sequence used to enable SDP must precede the data to be written. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP, and SDP will protect the AT28C040 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. The data in the enable and disable command sequences is not written to the device, and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. DEVICE IDENTIFICATION: An extra 256 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V 0.5V and using address locations 7FF80H to 7FFFFH, the bytes may be written to or read from in the same manner as the regular memory array. OPTIONAL CHIP ERASE MODE: The entire device can be erased using a 6-byte software erase code. Please see Software Chip Erase application note for details.
3
DC and AC Operating Range
AT28C040-20 Operation Read Operating Temperature (Case) VCC Power Supply Commercial Industrial Extended 0C - 70C -40C - 85C -55C - 125C 5V 10% Program 0C - 70C -40C - 85C -40C - 85C 5V 10% Read 0C - 70C -40C - 85C -55C - 125C 5V 10% AT28C040-25 Operation Program 0C - 70C -40C - 85C -40C - 85C 5V 10%
Operating Modes
Mode Read Write
(2)
CE VIL VIL VIH X X X
OE VIL VIH X
(1)
WE VIH VIL X VIH X X
I/O DOUT DIN High Z
Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms.
X VIL VIH
High Z
DC Characteristics
Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 A IOH = -100 A; VCC = 4.5V 2.4 4.2 2.0 0.45 Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC CE = VCC - 0.3V to VCC + 1V CE = 2.0V to VCC + 1V f = 5 MHz; IOUT = 0 mA Min Max 10 10 3 3 80 0.8 Units A A mA mA mA V V V V V
4
AT28C040
AT28C040
AC Read Characteristics
AT28C040-20 Symbol tACC tCE
(1) (2)
AT28C040-25 Min Max 250 250 0 0 0 55 55 Units ns ns ns ns ns
Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first
Min
Max 200 200
tOE
0 0 0
55 55
tDF(3)(4) tOH
AC Read Waveforms(1)(2)(3)(4)
Note:
1. 2. 3. 4.
CE May be delayed up to tACC - tCE after the address transition wihtout impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested.
Input Test Waveforms and Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T = 25C(1)
Symbol CIN COUT Note: Typ 4 8 Max 10 12 Units pF pF Conditions VIN = 0V VOUT = 0V
1. This parameter is characterized and is not 100% tested.
5
AC Write Characteristics
Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Min 0 50 0 0 100 50 0 Max Units ns ns ns ns ns ns ns
AC Write Waveforms
WE Controlled
CE Controlled
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AT28C040
AT28C040
Page Mode Characteristics
Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 Min Max 10 Units ms ns ns ns ns ns s ns
Page Mode Write Waveforms(1)(2)
Notes:
1. 2.
A8 through A18 must specify the page address during each high to low transition of WE (or CE). OE must be high only when WE and CE are both low.
7
Software Data Protection Enable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
Software Data Protection Disable Algorithm(1)
LOAD DATA AA TO ADDRESS 5555
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA 55 TO ADDRESS 2AAA
LOAD DATA A0 TO ADDRESS 5555
WRITES ENABLED(2)
LOAD DATA 80 TO ADDRESS 5555
LOAD DATA XX TO ANY ADDRESS(4)
LOAD DATA AA TO ADDRESS 5555
LOAD LAST BYTE TO LAST ADDRESS
ENTER DATA PROTECT STATE
LOAD DATA 55 TO ADDRESS 2AAA
Notes:
1. 2. 3. 4.
Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). Write Protect state will be activated at end of write even if no other data is loaded. Write Protect state will be deactivated at end of write period even if no other data is loaded. 1 to 256 bytes of data are loaded.
LOAD DATA 20 TO ADDRESS 5555
EXIT DATA PROTECT STATE(3)
LOAD DATA XX TO ANY ADDRESS(4)
LOAD LAST BYTE TO LAST ADDRESS
Software Protected Program Cycle Waveform(1)(2)(3)
Notes:
1. 2. 3.
A0 - A14 must conform to the addressing sequence for the first 3 bytes as shown above. After the command sequence has been issued and a page write operation follows, the page address inputs (A8 - A18) must be the same for each high to low transition of WE (or CE). OE must be high only when WE and CE are both low.
8
AT28C040
AT28C040
Data Polling Characteristics(1)
Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay
(2)
Min 10 10
Typ
Max
Units ns ns ns
Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.
0
ns
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns
Toggle Bit Waveforms(1)(2)(3)
Notes:
1. 2. 3.
Toggling either OE or CE or both OE and CE will operate toggle bit. Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary.
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Ordering Information(1)
tACC (ns) 200 ICC (mA) Active 80 Standby 3 Ordering Code AT28C040-20BC AT28C040-20FC AT28C040-20LC AT28C040-20BI AT28C040-20FI AT28C040-20LI AT28C040-20BI SL703 AT28C040-20FI SL703 AT28C040-20LI SL703 AT28C040-25BC AT28C040-25FC AT28C040-25LC AT28C040-25BI AT28C040-25FI AT28C040-25LI AT28C040-25BI SL703 AT28C040-25FI SL703 AT28C040-25LI SL703 Package 32B 32F 44L 32B 32F 44L 32B 32F 44L 32B 32F 44L 32B 32F 44L 32B 32F 44L Operation Range Commercial (0 to 70C) Industrial (-40 to 85C) Extended (See DC and AC Operating Range Table) Commercial (0 to 70C) Industrial (-40 to 85C) Extended (See DC and AC Operating Range Table)
80
3
80
3
250
80
3
80
3
80
3
Note:
1. See Valid Part Numbers.
Valid Part Numbers
The following table lists standard Atmel products that can be ordered.
Device Numbers AT28C040 AT28C040 Speed 20 25 Package and Temperature Combinations BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703 BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703
Die Products
Reference Section: Parallel EEPROM Die Products
Package Type 32B 32F 44L 32-Lead, 0.600" Wide, Ceramic Side Braze Dual Inline (Side Braze) 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package (Flatpack) 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Options Blank Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms
10
AT28C040
AT28C040
Packaging Information
32B, 32-Lead, 0.600" Wide, Ceramic Side Braze Dual Inline (Side Braze) Dimensions in Inches and (Millimeters) 32F, 32-Lead, Non-Windowed, Ceramic BottomBrazed Flat Package (Flatpack) Dimension in Inches and (Millimeters)
JEDEC OUTLINE MO-115
PIN #1 ID
.370(9.40) .270(6.86) .019(.482) .015(.381)
.829(21.1) .811(20.6) .050(1.27) BSC
.488(12.4) .472(12.0)
.045(1.14) MAX
.006(.152) .004(.101) .408(10.4) .355(9.02) .072(1.82) .030(0.76)
.120(3.05) .098(2.49)
.045(1.14) .026(.660)
44L, 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-5
*Ceramic lid standard unless specified. 11
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(c) Atmel Corporation 1998. Atmel Cor poration makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's website. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing
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0542B-10/98/xM
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